Python Developer (RTL generators)

Purpose
Our team develops a generator of Verilog components used in the CPU cluster: coherent interconnect and AXI crossbar. The tool is used to increase productivity of hardware developers and verificators. The tool is used to generate components of various configurations including large CPU clusters that integrate dozens of CPU cores, System Level Cache banks and peripheral devices connected with thousands of individual wires.

Responsibilities

• Development of new features, support for new hardware components
• Fixing bugs and maintenance of the RTL generator
• Verification of the generator
• Support and improvement of the automation infrastructure on Jenkins

Required qualifications

• Good Python knowledge, around 3+ years of experience.
• Experience with Linux development environment and Git.
• Technical English language: ability to read documentation, read and write Git commit messages.

Could be a plus:

• RTL hardware design or verification (Verilog, SystemVerilog etc.)
• Compiler design, data processing, transformation of model from one representation to another.
• Development of parsers for domain specific languages.

We offer:

• Become a part of the global process of transformation of microelectronics and create the latest RISC-V CPU, SoC and IP;
• Hybrid or remote format: you can work in a comfortable loft-office in Moscow (Trekhgornaya Manufactory) or Saint Petersburg (Polustrovo);
• Possibility to choose a convenient start and end of the working day;
• Competitive salary level (ready to appreciate your knowledge and experience) + performance bonuses;
• Training/certification by the company (according to the agreed plan);
• Ability to grow horizontally and vertically, and depending on results and interests to move between projects and teams;
• Voluntary medical insurance from the start day.